Flexible Service Solution灵活服务解决方案 Assembly 装配
Testing 试验 Wafer Bumping Overview 晶圆凸块概述 • Technology– 200mm wafer bumping in production (FCT licensee)– Developing 300mm wafer technology internally•技术-生产中的200mm晶圆凸块（FCT许可方）-内部开发300mm晶圆技术
• Facilities– DF-C for 200mm wafer bumping in production– CS-A facility is ready for 300mm wafer bumping• Capacity (200mm wafer)•设施-DF-C用于生产中的200mm晶圆凸块-CS-A设备已准备好进行300mm晶圆凸点•容量（200毫米晶圆）
Wafer Bumping Production Line 晶圆凸点生产线
Wafer Bumping Test Vehicle Die Size: 10X10 mm2 Pitch: 250 µ m (Area Array) Bumps: 1597 per Die Bump Materials: 63Sn37Pb, Low-α 63Sn37Pb, 90Pb10Sn 芯片尺寸：10X10 mm2 间距：250µm（面积阵列）凸点：每个芯片1597个
凸块材料：63Sn37Pb，低α 63Sn37Pb，90Pb10Sn
Bumped Wafer Bump Pattern
Outgoing Quality Check 出厂质量检查
Qualification chip: 10x10 mm2, 250 um array pitch, 1597 bumps/die, daisy-chain design芯片规格：10x10 mm2，250 um阵列间距，1597个凸点/芯片，菊花链设计
Reliability Test Results 可靠性试验结果
*Qualification package: 10x10 mm2 FC (250 um array pitch, 1597 bumps) on 27x27 mm2FCBGA 272 I/O, 2 layer BT sub., daisy-chain design*封装规格：27x27 mm2上的10x10 mm2 FC（250 um阵列间距，1597个凸点） FCBGA 272 I/O，2层BT子模块，菊花链设计 Bump Shear Results, after Multiple Reflows
• 220 deg. C maximum• Test vehicle: 10x10 mm2 die, 250 um area array, 1597 bumps/die• Results:(1) Bump shear data is stable even after 10 times reflow.(2) Failure mode: solder residue on die
•220摄氏度最大值 •测试车辆：10x10 mm2管芯、250 um面积阵列、1597个凸块/管芯 •结果： （1）即使回流10次，凸点剪切数据也是稳定的。 （2）失效模式：芯片上有焊料残留
Bump Shear Results, after High Temp. Storage
• Test vehicle: 20x22 mm2 die, 225 um array, 2217 bumps/die• Results:(1) Bump shear data is good and stable even after 500 hrs.(2) Failure mode check: solder residue on die.（1）即使在500小时后，冲击剪切数据也是良好和稳定的。 （2）故障模式检查：芯片上有焊料残留。
Flip Chip: Wafer Probing 倒装芯片：晶片探测
* Probe on Bump is suggested for volume production.*建议批量生产时使用凸块上的探头。Probe Mark Data 探针标记数据
Flip Chip Package Types 倒装芯片封装类型
FCCSP Package Outline FCCSP封装概述
Total height | 1.0 mm max | | Chip thickness | 0.28 mm* | | F/C Method | Solder bump |
| 0.36 mm | | Ball Pitch | 0.75 mm | | Solder Ball | 0.35 mm |
* Lapping capability on bumped wafer: 200 mm*凸点晶圆的研磨能力：200 mm
EHS-FCBGA Package Outline EHS-FCBGA封装概述
FCMCM Package Outline FCMCM封装概述
Total height
| 2.65 mm max | Chip thickness | 0.47 mm | F/C Method | Pb-free solder bump |
| 0.56 mm | Ball Pitch | 1.27 mm | Solder Ball | 0.89 mm |
Package Design Flow 封装设计流程
Assembly Process Flow 装配工艺流程
FCBGA Package Reliability Results FCBGA封装可靠性结果 z Pass JEDEC Level-3 Preconditioning (30 C/60% RH 192 hrs +3x Reflow at 220C) 通过JEDEC 3级预处理（室温30度/湿度60% 192小时 +220摄氏度下3次回流）
TCT: Condition B (-55/125°C)PCT: 121°C, 100%R H, 2atmHTS: 150°CTCT：条件B(-55/125°C） PCT：121°C，100%相对湿度，2atm HTS：150°C Summary of FCBGA Board Level Testing FCBGA板级测试综述 – 26x26 mm2 die, 40x40 mm2 HITCE / organic substrate– 3 types of HS (2pcs type / Cu, Cap type / AlSiC, Ring type / Cu)– Ball pitch / #: 1.0 mm / 1521– PCB: A4 size and 1.6 mm thick– Ball pad size / opening: 0.6 / 0.45 mm (SMD)– PCB pad size / opening: 0.45 / 0.6 mm (NSMD)-26x26 mm2芯片，40x40 mm2 HITCE/有机衬底 -3种HS（2pcs类型/铜、帽型/AlSiC、环型/铜） -球距/#:1.0mm/1521 -印刷电路板：A4尺寸和1.6毫米厚 -球垫尺寸/开口：0.6/0.45 mm(SMD) -PCB焊盘尺寸/开口：0.45/0.6 mm(NSMD)
– -40 / 125°C, 1 hr / cycle – Ramp up / down: 5/5 min, dwell time 25 min 试验条件：--40/125°C，1小时/周期循环-斜坡上升/下降：5/5分钟，停留时间25分钟
Board Level Testing Result Summary 板级测试结果汇总- Organic package has better solder joint life than ceramic package due to low CTE mismatch with PCB.
- Bare die package has better solder joint life than HS added package due to HS added package is more rigid than bare die package.
- Heat Spreader CTE effect
The smaller mismatch with PCB, the better solder joint life (Cu is better than AlSiC)Ring type is better than 2pc HS due to only 4 corners of ring type HS adhered to substrate, so this structure is not rigid as 2pc type.与PCB的失配越小，焊点寿命越长（Cu优于AlSiC） 环型优于2pc HS，因为环型HS只有4个角粘附在基底上，所以这种结构不像2pc型那样刚性。
Thermal Performance of FCBGA FCBGA的热性能 35x35 FCBGA with 10x10 mm2 thermal dieInput power: 5 W35x35 FCBGA，带10x10 mm2热管芯 输入功率：5 W
Electrical Performance Comparison of W/B PBGA versus F/C BGAW/B PBGA与F/C BGA的电性能比较
Assumption: 1. W/B BGA and F/C BGA use the same netlist. 2. Only shortest & lon gest traces are compared. 3. Wafer RDL(redistribution layer) paracitics is not inclu ded. 假设： 1.W/B BGA和F/C BGA使用相同的网表。
2.仅比较最短和最长轨迹。
3.不包括晶片RDL（再分布层）准晶。
Conclusion: 1. Electrical performance: F/C(2/2/2) > F/C(1/2/1) > W/B PBGA. 2. F/C BGA (1/2/1) has about 73% reduction for power/ground inductance, 35.8% reduction for traceind uctance due to no gold wire. 3. The major advantage of using F/C BGA on 4L PBGA will be the significant reduction on ground noise which may lead to 4×higher operating frequency than W/B 4L PBGA, if ground noise is the high frequency limitation. 结论： 1.电气性能：F/C(2/2/2)>F/C(1/2/1)>W/B PBGA。
2.F/C BGA（1/2/1）的电源/地电感降低了约73%，由于没有金线，迹线导纳降低了35.8%。
3.在4L PBGA上使用F/C BGA的主要优点是显著降低了接地噪声
如果接地噪声是高频限制，这可能导致工作频率比W/B 4L PBGA高4倍。
Flip Chip Package Roadmap 倒装芯片封装路线图
Future Development 未来发展 - Bump Pad Pitch Roadmap: 凸点焊盘间距路线图：
| Package Type | Bumping
| 2000
| 2001
| 2002
| FCCSP
| Peripheral, Solder | 180um | 125 um | 100 um | FCBGA
| Array, Solder | 225 um | 200 um | 180 um
|
Evaluate advanced substrate technology for high-end applications (PTFE, Thin Film) High-end FCBGA capability to larger package size (45x45mm2) and die size (30x30mm2) Advanced materials (No-flow underfill, Molded Underfill) 评估高端应用的先进基板技术（聚四氟乙烯、薄膜） 高端FCBGA功能，适用于更大的封装尺寸(45x45平方毫米）和芯片尺寸(30x30mm2） 先进材料（无流动底填料、模压底填料）
(FCCSP, FCBGA, EHS-FCBGA, High-end FCBGA,FCMCM); continually evolving new technologies to meet new demands. （FCCSP、FCBGA、EHS-FCBGA、高端FCBGA、FCMCM）；不断发展新技术以满足新需求。 来源：SMT之家
声明：本文由纳米家园转载，仅为了传达一种观点，并不代表对该观点的赞同或支持，若有侵权请联系我们将及时处理，谢谢。
| 
